The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a hole pattern using a double patterning process.
In a fabricating process for a DRAM smaller than a 50 nm process DRAM, it is difficult to fabricate a hole pattern due to limitations on a resolution of a photolithography apparatus. In such a fabrication of a hole pattern, a double patterning technology is used to form a hole. The double patterning technology forms a hole by forming a line in a crossing direction, where such technology is adapted for patterning rather than creating holes.
Recently, in a case where a low-temperature carbon is used as a hard mask, a dual hard mask of a Plasma Enhanced Tetra Ethyl Ortho Silicate (PETEOS) oxide layer and a silicon oxide nitride layer is used for patterning. At this time, the silicon oxide nitride layer, which is an upper layer of the dual hard mask, is etched first, and the PETEOS oxide layer, which is a lower layer of the dual hard mask, is etched using the etched silicon oxide nitride layer and a photoresist pattern as an etch barrier.
FIGS. 1A to 1D are perspective views illustrating a conventional method for forming a hole pattern.
Referring to FIG. 1A, an amorphous carbon layer 12, a PETEOS oxide layer 13, a silicon oxide nitride layer 14, and an anti-reflective coating (ARC) layer 15 are sequentially formed over an etch-target layer 11. The amorphous carbon layer 12 is used as a hard mask to etch the etch-target layer 11, the PETEOS oxide layer 13 is used as a basic hard mask during a double patterning process, and the silicon oxide nitride layer 14 is used as a hard mask to etch the PETEOS oxide layer 13.
A first photoresist pattern 16 is formed over the ARC layer 15. The first photoresist pattern 16 is formed as a line type in a first direction.
Subsequently, the ARC layer 15 and the silicon oxide nitride layer 14 are etched using the first photoresist pattern 16 as an etch barrier. Since the first photoresist pattern 16 is the line type, the ARC layer 15 and the silicon oxide nitride layer 14 are also formed as a line type in the first direction.
Referring to FIG. 1B, a silicon oxide nitride pattern 14A is formed by removing the first photoresist pattern 16 and the ARC layer 15 (shown in FIG. 1A).
Referring to FIG. 1C, a second photoresist pattern 17 is formed over a resultant structure including the silicon oxide nitride pattern 14A. The second photoresist pattern 17 may be formed as a line type in a second direction which is perpendicular to the first direction. Accordingly, a hole pattern is defined by the second photoresist pattern 17 and the silicon oxide nitride pattern 14A.
Referring to FIG. 1D, the PETEOS oxide layer 13 is etched using the second photoresist pattern 17 and the silicon oxide nitride pattern 14A as an etch barrier (shown in FIG. 1C), thereby forming a PETEOS oxide pattern 13A. The PETEOS oxide pattern 13A defines the hole pattern.
As described above, in the conventional method for forming the double hole pattern, the hole pattern is defined by the second photoresist pattern 17 and the silicon oxide nitride pattern 14A. However, since the conventional method uses different masks subject to the same etch conditions, etch characteristics may differ between the different masks, e.g., a Critical Dimension (CD) bias. Furthermore, when the PETEOS oxide layer is etched using the second photoresist pattern, a wiggling can occur due to characteristics of an etch process for an oxide layer, which has a high ion energy.
FIG. 2 is a picture showing a wiggling of the conventional method for forming the hole pattern.
Referring to FIG. 2, the wiggling 100 occurs in the second photoresist pattern used as an etch barrier during etching the PETEOS oxide layer.